Object structure

Title:

High level synthesis in FPGA of TCS/RNS converter

Creator:

Smyk, Robert ; Czyżak, Maciej

Subject and Keywords:

high–level synthesis ; residue number system ; FPGA ; C++ language ; two's complement–to–residue converter

Abstract:

The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.

Publisher:

Publishing House of Poznan University of Technology

Object type:

artykuł

ISBN/ISSN:

1897-0737

DOI:

10.21008/j.1897-0737.2017.91.0014

Language:

pol ; eng

Relation:

Strona czasopisma Politechnika Poznańska Wydział Elektryczny i Instytut Elektrotechniki i Elektroniki Przemysłowej

Rights Management:

Politechnika Poznańska

Format:

pp. 143-154

Rights:

wszystkie prawa zastrzeżone

Access rights:

dla wszystkich w zakresie dozwolonego użytku

Rights holder:

Politechnika Poznańska

Digital object format:

application/pdf